1. Field of Invention
The present invention is directed to an optical switch node. In particular, the present invention is directed to a self-routing switching node based on an optical associative memory and noncoherent pattern recognition techniques.
2. Description of Related Art
The increasing demand for high capacity communication links is being driven by data-intensive services on the Internet. For example, high capacity communications transmitted through links include multimedia information, multiparty video conferencing, video-on-demand, telemedicine, and database searching. Digital data transfer rates over commercial point-to-point fiber optic media currently run into the gigabit-per-second range, and will soon surpass the 10 Gb/s rate. While this represents an advance of just a single order of magnitude, the distinction between 1 Gb/s and 10 Gb/s is significant as the data rate for optically transmitted signals is currently overtaking the speed of commercially available electronics technology. Given the demand for multi-Gb/s speeds and the inability of conventional electronic equipment to keep pace with fiber optic transmission speeds, the development of novel Gb/s optoelectronic data processing components constitutes a critical technology area.
A significant amount of data is currently transmitted using the Asynchronous Transfer Mode (ATM) communications standard. ATM is a self-routing means of sending data over a network. Instead of relying on a single external controller to route data through the entire network from a source to a destination, ATM places a routing header of five bytes onto the front of a packet of data. The basic data unit in the ATM network is called a xe2x80x9ccellxe2x80x9d that has a fixed size of 53 bytes including a xe2x80x9cpayloadxe2x80x9d (the data portion) of 48 bytes and the xe2x80x9cheaderxe2x80x9d of 5 bytes. Each node in the network typically has a modest number of inputs and outputs (e.g., between 4 and 100). At each node in the network, the header information is read so that the node can autonomously decide where to send the packet next in the network. By consulting a switch routing table in the node, the packet xe2x80x9cfindsxe2x80x9d its way from its source to its final destination.
ATM technology has its history in the development of broadband ISDN in the 1970s and 1980s. From a technical view, ATM is an evolution of packet switching. Similar to packet switching for data (e.g., X.25, frame relay, transmission control protocol [TCP]/Internet protocol [IP]), ATM integrates the multiplexing and switching functions, and is typically a good match for bursty traffic (in contrast to circuit switching). Additionally, ATM allows communication between devices that operate at different speeds. Unlike packet switching, ATM generally supports high-performance, multimedia networking and has been implemented in a broad range of networking devices including PCs, workstations, server network interface cards, switched-Ethernet and token-ring workgroup hubs, workgroup and campus ATM switches, ATM enterprise network switches, ATM multiplexers, ATM-edge switches, and ATM-backbone switches.
ATM is also a capability that can be offered as an end-user service by service providers (as a basis for tariffed services) or as a networking infrastructure for these and other services. The most basic service building block is the ATM virtual circuit, which is an end-to-end connection that has defined end points and routes, but does not include dedicated bandwidth. Bandwidth is allocated on demand by the network as users have traffic to transmit.
The ATM connection standard organizes different streams of traffic in separate calls, thereby allowing the user to specify the resources required and the network to allocate resources based on these needs. Multiplexing multiple streams of traffic on each physical facility (between the end user and the network or between network switches), combined with the ability to send the streams to many different destinations, results in cost savings through a reduction in the number of interfaces and facilities required to construct a network.
ATM standards define (1) virtual path connections (VPCs), which contain (2) virtual channel connections (VCCs). A virtual channel connection (or virtual circuit) is the basic unit, which carries a single stream of cells, in order, from user to user. A collection of virtual circuits can be bundled together into a virtual path connection. A virtual path connection can be created from end-to-end across an ATM network. In this case, the ATM network does not route cells belonging to a particular virtual circuit. All cells belonging to a particular virtual path are routed the same way through the ATM network, thus resulting in faster recovery in case of major failures.
An ATM network also uses virtual paths internally for the purpose of bundling virtual circuits together between switches. Two ATM switches may have many different virtual channel connections between them, belonging to different users. These can be bundled by the two ATM switches into a virtual path connection that serves the purpose of a virtual trunk between the two switches. The virtual trunk is then handled as a single entity by, perhaps, multiple intermediate virtual path cross connects between the two virtual circuit switches.
Virtual circuits are statically configured as permanent virtual circuits (PVCs) or dynamically controlled via signaling as switched virtual circuits (SVCs). They can also be point-to-point or point-to-multipoint, thus providing a rich set of service capabilities. SVCs are often the preferred mode of operation in a network because they can be dynamically established, thereby minimizing reconfiguration complexity.
As discussed above, with the development of the ATM standard as the specification for a broadband communication network, the switching requirements of a network in terms of speed and function have increased significantly. In this regard, packet switching is based on the concept of statistical multiplexing onto the digital links, which implies that the use of large and very fast memories is of paramount importance. Even more important than the concept of statistical multiplexing is the fact that packet switching is performed on a packet-by-packet basis and not a connection-by-connection basis as with circuit switching. In circuit switched networks, the control memories of TSIs and TMSs are under the control of a central CPU that changes their configurations as connections are set up and torn down. With packet switching, however, each packet carries its own identifier called a xe2x80x9crouting tablexe2x80x9d that instructs the node where the packets have to be switched (routed). Therefore, a large amount of processing is required in a packet-switched node, and the connecting network of a packet switching node is likely to change its input/output connection pattern with a rate related to the transmission time of a packet. Based on the well-known seven layer protocol architecture of the OSI model, the routing function for classical X.25 low-speed networks belongs to the network layer, whereas the forwarding one is associated with the data link and physical layers.
Optical space switches are analogic devices that physically route an optical flow from an input to a selected output. Most of the present electronic switches are instead essentially based on the digital cross-points (e.g., based on CMOS, fast access RAM and electronic buffers). The optical switches are in a sense more similar to the earliest electromechanical or semi-electronic implementations of a crossbar network in the space domain than to the modern fully electronic switches operating both in the time and space domains.
Large switching matrices are composed by connecting small switching devices (switching elements) according to various architectures. Photonic space switching matrices are subdivided according to the kind of interconnection optical hardware being used (e.g., free-space, optical fibers or integrated optical waveguides). The networks are also classified according to the technology used to implement the switching elements.
Until recently, the rates at which data was transmitted over a fiber optic link and the speeds of electronic switching elements were roughly compatible. Fiber optic data rates of 155 Mb/s to 2.5 Gb/s corresponded well with the speed of high-end RISC microprocessors. In the past, therefore, it was reasonable to use such processors to read the routing headers from each of the incoming channels, decode them, and decide how to route the data back out to the network. While the speed of electronic microprocessors continues to advance at an impressive pace, the speed of fiber optic data links is also increasing at an impressive pace. Fiber optic links operating at 10 Gb/s and beyond are literally in a position to overtake and overwhelm even the most advanced electronic microprocessors.
This emerging disparity in speed between fiber optic data transmission and the microprocessors which route the data through a given communication network poses a serious technological problem. At each node of the network, high speed data piles up in buffers while the routing processor reads the header information from each channel and determines the appropriate switch settings to send the data further on its way through the network. Consider, for example, a node that routes 10 input channels to 10 output channels, where each channel carries data at a relatively modest rate of 10 Gb/s (e.g., the OC-192 rate). An ATM cell of 53 bytes takes roughly 42 nsec to arrive from start to finish, which is slightly less than 21 clock cycles of a 500 MHz microprocessor. It is unlikely that any microprocessor design could successfully route 10 channels in so few clock cycles (a more likely number of clock cycles is on the order of xcx9c2000). Even a 10-element parallel processor scheme can only result in a total of a xcx9c400 ns processing time, which is still ten times longer than the OC-192 ATM cell duration time of xcx9c42 ns.
Therefore, while the processor wastes time determining the appropriate routing for channels through a node, data continues to pile up in the node""s buffer. While sufficient memory may be integrated into receiver circuitry to accommodate the accumulated data while the processor makes routing decisions, it is clear that no amount of memory is sufficient after repeating this process an arbitrary number of times for bursty data. Therefore, the processor must make a routing decision in less time than it takes to load a subsequent ATM cell.
If data processing time is longer than 42 ns, a high-speed buffer memory is needed to store the next incoming ATM cell in each channel. Buffer memory with a large storage capacity is required to avoid ATM cell loss during peak network traffic. For an ATM network that operates at 10 Gb/s and beyond, electronic data processing techniques fall short of what is needed for efficient ATM network operation. Accordingly, the primary bottleneck in electronic ATM switches is the slow data processing speed.
Photonic processing techniques such as time division multiplexing (TDM), wavelength division multiplexing (WDM), code division multiplexing (CDM), and their combinations are often used for self-routing. These conventional self-routing techniques determine routing control signals based only on header information embedded by a different time slot, a different optical wavelength, or a different code sequence, rather than by an address-bit field defined in the ATM network standard. Thus, it is difficult to retrofit these photonic techniques into the ATM network operation. The range of switching times achievable by these photonic techniques indicates that optical space and wavelength switching is more suitable for circuit switching than for packet switching networks (especially if packets are as short as in ATM).
Furthermore, these photonic processing techniques cannot handle switching contention problems when more than one header has the same forwarding address (e.g., the same time allocation in TDM, the same wavelength channel allocation in WDM, or the same code sequence in CDM). Therefore, this switching contention problem significantly degrades the performance of a self-routing switching node.
Finally, these conventional techniques cannot handle multiple-hop stage networks. By inserting particular header information into a data packet stream, a switching node can determine the switching function and switch a given input channel to a given output channel in one stage. When there are multiple hops in the network, as there often are in self-routing networks, advanced technologies such as all-optical time slot interchange, all-optical wavelength converters, and all-optical code sequence converters are needed. Unfortunately, these all-optical technologies are still primarily in the research and development stage.
It is an object of this invention to provide a self-routing switching node that includes an optical associative memory that receives packet header information, and a switching array that is coupled to the optical associative memory and receives control signals from the optical associative memory.
Yet another object of this invention is to provide a method of operating a self-routing switching node including the steps of receiving header information for a data packet, transmitting the header information through an optical mask, detecting routing information based on the header information transmitted through the optical mask, and transmitting control information to a switch based on the detected routing information.
Another object of this invention is to provide a light imaging quasi-orthogonal self-routing switching node including a header coding module that transforms a set of header data associated with a data packet from an electrical signal into an optical signal, an electro-optic page composer module that receives the optical signal from the header coding module, an image spatial fan-out distribution module that distributes the optical signal from the electro-optic page composer, and an image recognition module that routes the set of header data to a destination address.
Yet another object of this invention is to provide a self-routing switching node including a plurality of input fibers including a set of data packets, a buffer memory unit wherein the set of data packets is temporarily stored and wherein a set of header bits associated with each data packet in the set of data packets is copied, an optical heteroassociative data mapping processor that processes the copied set of header bits by converting a given input pattern into a corresponding output pattern based on a desired mapping algorithm, generates a set of memory control signals, and transmits the set of memory control signals to the buffer memory unit to access a set of desired data packets, and a switching array that receives the set of data packets from the plurality of output communication ports and routes the set of data packets based on a set of routing control signals from the data mapping processor.
Another object of this invention is to provide a self-routing switching node including a plurality of input fibers including a set of optical data packets, a plurality of input communication ports that convert the set of optical data packets into a set of electrical data packets, a buffer memory unit wherein the set of electrical data packets is temporarily stored and wherein a set of header bits associated with each data packet in the set of electrical data packets is copied, an optical heteroassociative data mapping processor that processes the copied set of header bits by converting a given input pattern into a corresponding output pattern based on a desired mapping algorithm, generates a set of memory control signals, and transmits the set of memory control signals to the buffer memory unit to access a set of desired data packets, a plurality of output communication ports that converts the set of desired electrical data packets into an optical set of data packets, and a switching array that receives the optical set of data packets from the plurality of output communication ports and routes the optical set of data packets based on a set of routing control signals from the data mapping processor.
Yet another object of this invention is to provide a self-routing switching node including a plurality of input fibers including a set of data packets, a buffer memory unit wherein the set of data packets is temporarily stored and wherein a set of header bits associated with each data packet in the set of data packets is copied, an optical digital heteroassociative data mapping processor that processes the copied set of header bits by converting a given input pattern into a corresponding output pattern based on a desired mapping algorithm, generates a set of memory control signals, and transmits the set of memory control signals to the buffer memory unit to access a set of desired data packets, and a switching array that receives the set of data packets from the plurality of output communication ports and routes the set of data packets based on a set of routing control signals from the data mapping processor.
Another object of this invention is to provide a data mapping processor including a header input including a plurality of light beams representing a set of header data corresponding to a data packet, a microlens array that collimates the plurality of light beams, a decoding mask that diffracts the plurality of collimated light beams based on a predesigned coding sequence, a photodetector array that detects the plurality of diffracted light beams, and a heteroassociative memory processing circuit that converts a given input pattern into a corresponding output pattern based on a desired mapping algorithm.
Yet another object of this invention is to provide a data mapping processor including a header input including a plurality of multiple channel electrical signals representing a set of header data corresponding to a data packet, a laser diode array that transforms the plurality of electrical signals into a plurality of light beams, a microlens array that collimates the plurality of light beams, a decoding mask that diffracts the plurality of collimated light beams based on a predesigned coding sequence, a photodetector array that detects the plurality of diffracted light beams, and a heteroassociative memory processing circuit that converts a given input pattern into a corresponding output pattern based on a desired mapping algorithm.